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Data Sheet No. PD94124
IRU1030
3A LOW DROPOUT POSITIVE ADJUSTABLE REGULATOR DESCRIPTION
The IRU1030 is a low dropout three-terminal adjustable regulator with minimum of 3A output current capability. This product is specifically designed to provide well regulated supply for low voltage IC applications such as Pentium P54C, P55C as well as GTL+ termination for Pentium Pro and Klamath processor applications. The IRU1030 is also well suited for other processors such as Cyrix, AMD and Power PC applications. The IRU1030 is guaranteed to have <1.3V dropout at full load current making it ideal to provide well regulated outputs of 2.5V to 3.3V with 4.75V to 7V input supply.
FEATURES
Guaranteed < 1.3V Dropout at Full Load Current Fast Transient Response 1% Voltage Reference Initial Accuracy Output Current Limiting Built-In Thermal Shutdown
APPLICATIONS
Low Voltage Processor Applications such as: P54C, P55C, Cyrix M2, POWER PC, AMD GTL+ Termination PENTIUM PRO, KLAMATH Low Voltage Memory Termination Applications Standard 3.3V Chip Set and Logic Applications
TYPICAL APPLICATION
5V
C1 1500uF Vin
3
IRU1030
Vout
2
R1 121
3.3V / 3A
C2 1500uF
Adj
1
R2 200
1030app1-1.1
Figure 1 - Typical Application of IRU1030 in a 5V to 3.3V regulator
Notes: Pentium P54C, P55C, Klamath, Pentium Pro, VRE are trademarks of Intel Corp.Cyrix M2 is trademark of Cyrix Corp. Power PC is trademark of IBM Corp.
PACKAGE ORDER INFORMATION
Tj (C) 0 To 150 3-PIN PLASTIC TO-220 (T) IRU1030CT 3-PIN PLASTIC TO-263 (M) IRU1030CM 2-PIN PLASTIC TO-252 (D-Pak) IRU1030CD
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IRU1030
ABSOLUTE MAXIMUM RATINGS
Input Voltage (Vin) .................................................... Power Dissipation ..................................................... Storage Temperature Range ...................................... Operating Junction Temperature Range ..................... 7V Internally Limited -65C To 150C 0C To 150C
PACKAGE INFORMATION
3-PIN PLASTIC TO-220 (T)
FRONT VIEW 3
3-PIN PLASTIC TO-263 (M)
FRONT VIEW
2-PIN PLASTIC TO-252 (D-Pak)
FRONT VIEW 3
Vin Vout Adj
3
Vin Vout Adj Tab is Vout
Vin
Tab is Vout
2
Tab is Vout
2
1
1
1
Adj
JT=2.7C/W JA=60C/W
JA=35C/W for 1" Square pad
JA=70C/W for 0.5" Square pad
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over Cin=1F, Cout=10F, and Tj=0 to 150!C. Typical values refer to Tj=25!C. PARAMETER Reference Voltage Line Regulation Load Regulation (Note 1) Dropout Voltage (Note 2) Current Limit Minimum Load Current (Note 3) Thermal Regulation Ripple Rejection Adjust Pin Current Adjust Pin Current Change Temperature Stability Long Term Stability RMS Output Noise SYM Vref TEST CONDITION MIN TYP Io=10mA, Tj=25!C, (Vin-Vo)=1.5V 1.238 1.250 Io=10mA, (Vin-Vo)=1.5V 1.225 1.250 Io=10mA, 1.3V<(Vin-Vo)<7V Vin=3.3V, Vadj=0, 10mAVo
Iadj
Note 1: Low duty cycle pulse testing with Kelvin connections is required in order to maintain accurate data. Note 2: Dropout voltage is defined as the minimum differential voltage between Vin and Vout required to maintain regulation at Vout. It is measured when the output voltage drops 1% below its nominal value.
Note 3: Minimum load current is defined as the minimum current required at the output in order for the output voltage to maintain regulation. Typically the resistor dividers are selected such that this current is automatically maintained.
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IRU1030
PIN DESCRIPTIONS
PIN # 1 2 3 PIN SYMBOL Adj Vout Vin PIN DESCRIPTION A resistor divider from Vout to Adj pin to ground sets the output voltage. The output of the regulator. A minimum of 10F capacitor must be connected from this pin to ground to insure stability. The input pin of the regulator. Typically a large storage capacitor is connected from this pin to ground to insure that the input voltage does not sag below the minimum drop out voltage during the load transient response. This pin must always be 1.3V higher than Vout in order for the device to regulate properly.
BLOCK DIAGRAM
Vin 3 2 Vout
+
1.25V CURRENT LIMIT THERMAL SHUTDOWN
+
1030blk1-1.0
1 Adj
Figure 2 - Simplified block diagram of the IRU1030
APPLICATION INFORMATION
Introduction The IRU1030 adjustable Low Dropout (LDO) regulator is a three-terminal device which can easily be programmed with the addition of two external resistors to any voltages within the range of 1.25 to 5.5V. This regulator unlike the first generation of the three-terminal regulators such as LM117 that required 3V differential between the input and the regulated output, only needs 1.3V differential to maintain output regulation. This is a key requirement for today's microprocessors that need typically 3.3V supply and are often generated from the 5V supply. Another major requirement of these microprocessors such as the Intel P54C is the need to switch the load current from zero to several amps in tens of nanoRev. 1.1 06/29/01
seconds at the processor pins, which translates to an approximately 300 to 500ns current step at the regulator. In addition, the output voltage tolerances are also extremely tight and they include the transient response as part of the specification. For example Intel VRE specification calls for a total of 100mV including initial tolerance, load regulation and 0 to 4.6A load step. The IRU1030 is specifically designed to meet the fast current transient needs as well as providing an accurate initial voltage, reducing the overall system cost with the need for fewer output capacitors.
3
IRU1030
Output Voltage Setting The IRU1030 can be programmed to any voltages in the range of 1.25V to 5.5V with the addition of R1 and R2 external resistors according to the following formula: VOUT = VREF x o1 + R2 p + IADJ x R2 R1 regulator and the load is gained up by the factor of (1+R2/ R1), or the effective resistance will be, Rp(eff)=Rp*(1+R2/ R1). It is important to note that for high current applications, this can represent a significant percentage of the overall load regulation and one must keep the path from the regulator to the load as short as possible to minimize this effect.
PARASITIC LINE RESISTANCE
Where: VREF = 1.25V Typically IADJ = 50A Typically R1 and R2 as shown in figure 3:
Rp
Vin
Vin
Vin Vout
Vin
Vout
Vout
IRU1030
Adj R1 RL
IRU1030
Adj Vref IAdj = 50uA R1
R2
R2
1030app2-1.0
1030app3-1.0
Figure 3 - Typical application of the IRU1030 for programming the output voltage The IRU1030 keeps a constant 1.25V between the output pin and the adjust pin. By placing a resistor R1 across these two pins a constant current flows through R1, adding to the Iadj current and into the R2 resistor producing a voltage equal to the (1.25/R1)*R2 + Iadj*R2 which will be added to the 1.25V to set the output voltage. This is summarized in the above equation. Since the minimum load current requirement of the IRU1030 is 10mA, R1 is typically selected to be 121 resistor so that it automatically satisfies the minimum current requirement. Notice that since Iadj is typically in the range of 50A it only adds a small error to the output voltage and should only be considered when a very precise output voltage setting is required. For example, in a typical 3.3V application where R1=121 and R2=200 the error due to Iadj is only 0.3% of the nominal set point. Load Regulation Since the IRU1030 is only a three-terminal device, it is not possible to provide true remote sensing of the output voltage at the load. Figure 4 shows that the best load regulation is achieved when the bottom side of R2 is connected to the load and the top side of R1 resistor is connected directly to the case or the Vout pin of the regulator and not to the load. In fact, if R1 is connected to the load side, the effective resistance between the
Figure 4 - Schematic showing connection for best load regulation Stability The IRU1030 requires the use of an output capacitor as part of the frequency compensation in order to make the regulator stable. Typical designs for microprocessor applications use standard electrolytic capacitors with a typical ESR in the range of 50 to 100m and an output capacitance of 500 to 1000F. Fortunately as the capacitance increases, the ESR decreases resulting in a fixed RC time constant. The IRU1030 takes advantage of this phenomena in making the overall regulator loop stable. For most applications a minimum of 100F aluminum electrolytic capacitor such as Sanyo MVGX series, Panasonic FA series as well as the Nichicon PL series insures both stability and good transient response. Thermal Design The IRU1030 incorporates an internal thermal shutdown that protects the device when the junction temperature exceeds the maximum allowable junction temperature. Although this device can operate with junction temperatures in the range of 150!C, it is recommended that the selected heat sink be chosen such that during maximum continuous load operation the junction temperature is kept below this number. The example below shows the steps in selecting the proper regulator heat sink for the GTL+ terminator using a separate regulator for each end.
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IRU1030
Assuming the following specifications: VIN = 3.3V VOUT = 1.5V IOUT(MAX) = 2.7A TA = 35!C The steps for selecting a proper heat sink to keep the junction temperature below 135C is given as: 1) Calculate the maximum power dissipation using: PD = IOUT x (VIN - VOUT) PD = 2.7 x (3.3 - 1.5) = 4.86W 2) Select a package from the regulator data sheet and record its junction to case (or tab) thermal resistance. Selecting TO-220 package gives us: JC = 2.7!C/W 3) Assuming that the heat sink is black anodized, calculate the maximum heat sink temperature allowed: Assume, cs=0.05C/W (heat-sink-to-case thermal resistance for black anodized) TS = TJ - PD x (JC + CS) TS = 135 - 4.86 x (2.7 + 0.05) = 121.7!C 4) With the maximum heat sink temperature calculated in the previous step, the heat-sink-to-air thermal resistance (SA) is calculated by first calculating the temperature rise above the ambient as follows: T = TS - TA = 121.7 - 35 = 86.7!C T=Temperature Rise Above Ambient SA = T 86.7 = = 17.8!C/W PD 4.86 AAVID................PH# (603) 528 3400 Thermalloy..........PH# (214) 243-4321 Designing for Microprocessor Applications As it was mentioned before the IRU1030 is designed specifically to provide power for the new generation of the low voltage processors requiring voltages in the range of 2.5V to 3.6V generated by stepping down the 5V supply. These processors demand a fast regulator that supports their large load current changes. The worst case current step seen by the regulator is anywhere in the range of 1 to 7A with the slew rate of 300 to 500ns which could happen when the processor transitions from "Stop Clock" mode to the "Full Active" mode. The load current step at the processor is actually much faster, in the order of 15 to 20ns, however the decoupling capacitors placed in the cavity of the processor socket handle this transition until the regulator responds to the load current levels. Because of this requirement the selection of high frequency low ESR and low ESL output capacitors is imperative in the design of these regulator circuits. Figure 5 shows the effects of a fast transient on the output voltage of the regulator. As shown in this figure, the ESR of the output capacitor produces an instantaneous drop equal to the (VESR=ESR*I) and the ESL effect will be equal to the rate of change of the output current times the inductance of the capacitor. (VESL =L*I/t). The output capacitance effect is a droop in the output voltage proportional to the time it takes for the regulator to respond to the change in the current, (VC = t * I / C ) where t is the response time of the regulator. Air Flow (LFM) 0 100 200 300 Thermalloy 6109PB 6110PB 7141 7178 AAVID 575002 507302 576802B 577102 Note: For further information regarding the above companies and their latest product offerings and application support contact your local representative or the numbers listed below:
5) Next, a heat sink with lower sa than the one calculated in step 4 must be selected. One way to do this is to simply look at the graphs of the "Heat Sink Temp Rise Above the Ambient" vs. the "Power Dissipation" and select a heat sink that results in lower temperature rise than the one calculated in the previous step. The following heat sinks from AAVID and Thermalloy meet this criteria.
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IRU1030
V ESR V ESL T
LOAD CURRENT
2) With the output capacitance being 1500F:
VC
Vc =
t x I 2 x 2.7 = = 3.6mV 1500 C
Where: t = 2s is the regulator response time
1030plt1-1.0
To set the output DC voltage, we need to select R1 and R2:
LOAD CURRENT RISE TIME
Figure 5 - Typical regulator response to the fast load current step An example of a regulator design to meet the Intel Pentium Pro GTL+ specification is given below. Assume the specification for the processor as shown in Table 1: Type of Vout Processor Nominal Pentium Pro 1.50 V Imax 2.7 A Max Allowed Output Tolerance 150 mV
3) Assuming R1 = 121, 0.5% 1.5 VOUT R2 =o - 1px R1 =o - 1px 121 = 24.2 o p o p 1.25 VREF Select R2 = 24.3, 0.5% Selecting both R1 and R2 resistors to be 0.5% tolerance, results in the least amount of error introduced by the resistor dividers leaving 1.3% error budget for the IRU1030 reference which is within the initial accuracy of the device. Finally, the input capacitor is selected as follows: 4) Assuming that the input voltage can drop 150mV before the main power supply responds, and that the main power supply response time is 50s, then the minimum input capacitance for a 2.7A load step is given by: CIN = 2.7 x 50 = 900F 0.15
Table 1 - GTL+ Specification for Pentium Pro The first step is to select the voltage step allowed in the output due to the output capacitor's ESR: 1) Assuming the regulator's initial accuracy plus the resistor divider tolerance is 30 mV (2% of 1.5V nominal), then the total step allowed for the ESR and the ESL, is -120 mV. Assuming that the ESL drop is -10mV, the remaining ESR step will be -110mV. Therefore the output capacitor ESR must be: ESR 110 = 40m 2.7
The ESR should be less than: ESR = (VIN - VOUT - V - VDROP) I
The Sanyo MVGX series is a good choice to achieve both price and performance goals. The 6MV1500GX, 1500F, 6.3V has an ESR of less than 36m typ. Selecting a single capacitor achieves our design goal. The next step is to calculate the drop due to the capacitance discharge and make sure that this drop in voltage is less than the selected ESL drop in the previous step.
Where: VDROP L Input voltage drop allowed in step 4 V L Maximum regulator dropout voltage I L Load current step ESR = (3.3 - 1.5 - 1.2 - 0.15) = 0.16 2.7
Selecting a single 1500F the same type as the output capacitors exceeds our requirements. However, the same input capacitor can also support the second regulator for the other end of termination.
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IRU1030
Figure 6 shows the completed schematic for our example.
3.3V
C1 1500uF Vin Vout
1.5V
C2 1500uF R1 121 0.5% R2 24.3 0.5% R3 150 0.5% R4 75 0.5%
IRU1030
Adj
Layout Consideration The output capacitors must be located as close to the Vout terminal of the device as possible. It is recommended to use a section of a layer of the PC board as a plane to connect the Vout pin to the output capacitors to prevent any high frequency oscillation that may result due to excessive trace inductance.
Vref
1030app4-1.2
Figure 6 - Final schematic for half of the GTL+ termination regulator
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IRU1030
Notes
IR WORLD HEADQUARTERS : 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. Data and specifications subject to change without notice. 02/01
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Rev. 1.1 06/29/01

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